One dimensional t.d.i operation solid-state imager

ABSTRACT

A one-dimensional time-delay integration solid-state imager includes a plurality of light-to-electricity conversion parts which store signal charges generated in response to incident light, a vertical CCD corresponding to a series of the light-to-electricity conversion parts for transferring stored signal charges, and a gate for controlling transfer of signal charges stored at the light-to-electricity conversion parts to the vertical CCD. The signal charges corresponding to the same observed image moving on the plurality of light-to-electricity conversion parts are added to enhance the signal-to-noise ratio, and a background signal charge removing region for removing background signal charges is provided at the vertical CCD for removing background charges during the transfer of signal charges.

FIELD OF THE INVENTION

The present invention relates to a one-dimensional solid-state imagerwith time-delay integration and more particularly to an improvement inthe performance thereof.

BACKGROUND OF THE INVENTION

Conventionally when a one-dimensional solid-state imager is used toobserve an object that moves at a high speed, there is a problem in thatthe signal-to-noise ratio of an output signal is reduced. This isbecause the storage time of signal charges at the light-to-electricityconversion part is too short and the signal charge amount correspondingto the observed image is too small. In order to solve this problem, itis proposed to enhance the signal-to-noise ratio of the output signal byadding signal charges corresponding to the same observed image to signalcharges produced by observed images that move on thelight-to-electricity conversion part. Such operation is called T.D.I.(Time-Delay Integration) operation and this operation is effective onlyin the one-dimensional solid-state imager. A solid-state imager ofT.D.I. operation type will be described with reference to the drawings.

FIG. 3 shows a construction of a prior art one-dimensional T.D.I. typesolid-state imager. In FIG. 3, a light-to-electricity conversion part 1is provided for storing signal charges which are generated in accordancewith the light incident to the imager. A vertical charge transfer part(hereinafter referred to as vertical CCD) constituted by a chargecoupled device (hereinafter referred as CCD) is provided fortransferring charges generated at the light-to-electricity conversionpart 1 in the vertical direction. A horizontal charge transfer part 3(hereinafter referred to as a horizontal CCD) is provided for receivingsignal charges transferred by the vertical CCD 2 and transferring thesame in the horizontal direction. A transfer gate 4 is provided betweenthe light-to-electricity conversion part 1 and the vertical CCD 2 forcontrolling the transfer of the signal charges at thelight-to-electricity conversion part 1 to the vertical CCD 2. An outputpart 5 is provided for outputting the signal charges transferred by thehorizontal CCD 3. Here, the arrow M represents the direction in whichthe observed image focused on the imager moves. Reference characters Ato D designate regions on which a part of the observed image is focused.

Now, it is assumed that a part of the observed image is focused on theregion A. When a part of the observed image is supposed to be O₁, signalcharges in accordance with the observed image O₁ are stored at thelight-to-electricity conversion part 1. The stored signal charges areread out to the vertical CCD 2 by turning on the transfer gate 4 whilethe observed image O₁ moves from the region A to the region B. The readout signal charges are transferred in the vertical CCD 2 in the verticaldirection. The transfer speed then is equal to the velocity of theobserved image.

Subsequently thereto, after the observed image O₁ has reached the regionB, signal charges corresponding to the observed image O₁ are stored atthe light-to-electricity conversion part 1 of the region B. The amountof the stored signal charges is equal to the signal charges stored atthe light-to-electricity conversion part 1 of the region A. Then, thenext observed image O₂ is focused on the region A. Then signal chargesstored at the light-to-electricity conversion part 1 of the region B areread out to the vertical CCD 2 from the light-to-electricity conversionpart 1 by turning on the transfer gate becomes "ON" state while theobserved image O₁ moves to the region C from the region B after apredetermined storage time, and are added to the signal charges read outat the region A which are transferred to this part of the vertical CCD2. In this way, the total signal charge amount corresponding to theobserved image O₁ is doubled. Accordingly, when this operation isrepeated n times with n light-to-electricity conversion parts 1 in thevertical direction, the signal charge amount is multiplied n times andthe shot noise becomes √n times. The signal charges thus accumulated ntimes in the charge amount in the vertical CCD 2 are moved to thehorizontal CCD 3 and transferred to the output part 5 to be output.

When the T.D.I. operation is repeated n times in this way, thesignal-to-noise ratio in the vertical CCD 2 is improved by √n times.

In the prior art one-dimensional solid-state imager carrying out T.D.I.operation, when n light-to-electricity conversion parts are used, ntimes the original signal charge is stored at the part of the verticalCCD relative to those which do not carry out T.D.I. operation. However,if the capacity of the vertical CCD is equal to that of the prior artone-dimensional solid-state imager, an overflow of charges arises in thevertical CCD and the observed image is not correctly recognized, andblooming results. If the capacitance of CCD is assumed to be inproportion to the area of the vertical CCD, this means that the area ofthe vertical CCD is increased. When a fundamental cell (hereinafterreferred to as a pixel) is assumed to be constituted by thelight-to-electricity conversion part, the transfer gate correspondingthereto, and the vertical CCD, the numerical aperture, which is areference value of sensitivity in the general solid-state imager isdefined as in the following. That is, the numerical aperture is a ratioof the area which is occupied by the light-to-electricity conversionpart to the total pixel area. From this value, it is apparent that asthe area other than the light-to-electricity conversion part becomessmall inside the pixel, the numerical aperture is increased and thesensitivity is also increased. Accordingly, in the prior art devicecarrying out T.D.I. operation, when the area of the vertical CCD isincreased to prevent blooming, the numerical aperture is reduced and, asa result, enhancement of sensitivity which is an object of the T.D.I.operation is prevented.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a one-dimensionalsolid-state imager using T.D.I. operation with enhanced sensitivitywithout lowering the numerical aperture.

Other objects and advantages of the present invention will becomeapparent from the detailed description given hereinafter; it should beunderstood, however, that the detailed description and specificembodiment are given by way of illustration only, since various changesand modifications within the spirit and the scope of the invention willbecome apparent to those skilled in the art from this detaileddescription.

In accordance with the present invention, in a T.D.I. operation typesold-state imager, a region for removing charges corresponding to thebackground light component included in the signal charges that aresuccessively increased by the T.D.I. operation while being transferredin the vertical CCD is provided in the vertical CCD. Therefore, signalcharges read out of the light-to-electricity conversion part haveremoved each time the charges are transferred the background signalcharges in the vertical CCD, so that the increase in the signal chargesin the vertical CCD is suppressed to the lowest amount and as a result,a T.D.I. operation type solid-state imager having a good operationsensitivity is obtained.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a construction of a T.D.I. operation typesolid-state imager in accordance with an embodiment of the presentinvention;

FIG. 2 is a diagram showing a detailed construction of a backgroundsignal charge removing part of the T.D.I. operation type solid-stateimager of FIG. 1;

FIG. 3 is a diagram showing a construction of a prior art solid-stateimager;

FIGS. 4(a) and 4(b) are diagrams showing cross-sectional views alonglines I-II, and X-Y of FIG. 2, respectively;

FIG. 5 is a diagram showing the timing of clock pulses applied to thegate electrodes of the T.D.I. operation type solid-state imager of FIG.2;

FIG. 6 is a diagram showing potentials of the background signal chargeremoving part of the T.D.I. operation type solid-state imager of FIG. 2;

FIG. 7 is a diagram showing a construction of a background signalremoving part of the T.D.I. operation type solid-state imager of FIG. 1;

FIGS. 8(a) and 8(b) are cross-sectional views along lines I-II, and X-Yof FIG. 7, respectively;

FIG. 9 is a diagram showing the timing of clock pulses applied to thegate electrodes of the T.D.I. operation type solid-state imager inaccordance with another embodiment of the present invention;

FIG. 10 is a diagram showing potentials of the background signal chargeremoving part of the T.D.I. operation type solid-state imager of FIG. 9;and

FIG. 11 is a diagram showing a construction of a T.D.I. operation typesolid-state imager in accordance with a third embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An embodiment of the present invention will be described in detail withreference to the drawings.

FIG. 1 is a diagram showing a construction of a T.D.I. operation typesolid-state imager in accordance with a first embodiment of the presentinvention. In FIG. 1 the same reference numerals designate the same orcorresponding parts as those shown in FIG. 3. Numeral 6 designates abackground signal removing part which is provided at an appropriateposition of the CCD. In the figure, the arrow M designates a directionin which the observed image which is focused on the imaging devicemoves. Reference characters A to E designate regions where a part of theobserved image is focused.

FIG. 2 shows a detailed construction of the background signal chargeremoving part 6 shown in FIG. 1. In FIG. 2, vertical CCD gate electrodes10 to 13 are provided for controlling signal charge transfer in thevertical CCD 2. An n type region 14 is provided for transferring signalcharges in the vertical CCDs 10 to 13. A storage gate electrode 21 isprovided for storing signal charges transferred to the background signalcharge removing part 6. A charge removal control gate electrode 23 isprovided for removing background signal charges from the signal chargestransferred from the vertical CCD. A drain region (n type region) 24 isprovided for transferring signal charges removed by the control gateelectrode 23.

FIGS. 4(a) and 4(b) show cross-sections along lines I-II, X-Y of FIG. 2,respectively. Numeral 31 designates a gate oxide film and numeral 32designates a vertical CCD. Numeral 33 designates a p type semiconductorsubstrate and numeral 34 designates a separating oxide film.

A description is given of the operation hereinafter.

Now it is supposed that a part of the observed image is focused on theregion A. When the part of the observed image is assumed to be O₁,charges in accordance with the observed image O₁ are stored at thelight-to-electricity conversion part 1 of the region A. These storedcharges are read out to the vertical CCD 2 when the transfer gate 4 isturned on while the observed image O₁ is moving to the region B from theregion A. The read out signal charges are transferred in the verticalCCD 2 in the vertical direction. The transfer speed then is equal to themoving speed of the observed image.

Subsequently thereto, when the observed image O₁ reaches the region B,signal charges in accordance with the observed image O₁ are stored atthe light-to-electricity conversion part 1 of the region B. Then, thenext observed image O₂ is focused on the region A. The signal chargesstored at the light-to-electricity conversion part 1 of the region B areread out to the vertical CCD 2 from the light-to-electricity conversionpart 1 when the transfer gate is turned on at a time when signal chargesread out from the region A, while the observed image O₁ moves from theregion B to the region C, are transferred to a part of the vertical CCD2 corresponding to the light-to-electricity conversion part 1 of theregion B, and added to the signal charges read out at the region A.Thereby, the signal charge amount corresponding to the observed image O₁is doubled. An operation similar to that in the region B occurs at theregion C, and signal charges in accordance with the observed image O₁are added at the part of the vertical CCD 2 in accordance with thelight-to-electricity conversion part 1 of the region C, amounting tothree times the original charge amount. These signal charges aretransferred in the vertical CCD 2 in the vertical direction at the samespeed as that of the moving speed of the observed image O₁ while theobserved image O₁ moves from the region C to the region D, and extrasignal charges are removed by the background signal charge removing part6.

A description is given of the operation of the background signal chargeremoving part 6 with reference to FIGS. 5 and 6. FIG. 5 shows the timingat which clock pulses are applied to respective gate electrodes in FIG.2. The clock pulse φ₁ is applied to the gate electrodes 10 and 12, theclock pulse φ₂ is applied to the gate electrodes 11 and 13, the clockpulse φ₃ is applied to the storage electrode 21, the clock pulse φ₄ isapplied to the charge transfer control electrode 22, and the clock pulseφ₅ is applied to the charge removal control gate electrode 23. FIG. 6shows a potential diagram in accordance with FIG. 2. In FIG. 6,reference characters T₁ to T₇ correspond to times T₁ to T₇ in FIG. 5.Reference characters a, b, and c designate signal charges and arepresents signal charges which have increased by the T.D.I. operation,b represents background signal charges, and c represents signal chargesafter the background signal charges b are removed.

At time T₁, the clock pulses φ₁ and φ₂ applied to the gate electrodes 10and 11 are high voltages and a potential well is produced at and belowthese gate electrodes. Signal charges which are transferred by thevertical CCD 2 are stored at the well.

During the period from time T₁ to time T₂, the voltage of the clockpulse φ₁ is lowered and the voltage of the clock pulse φ₃ is raised andaccompanying therewith the potential below the gate electrode 10 israised and the potential below the storage gate electrode 21 is lowered.Thereby, the potential well changes as shown in the figure and as aresult, the signal charges move to below the gate electrodes 11 and 21from below the gate electrodes 10 and 11.

During the period from time T₂ to timing T₃, the voltage of the clockpulse φ₂ is lowered and the voltage of the clock pulse φ₄ is raised.Accompanying therewith, the potential wells change as shown in thedrawing. Then, the voltage of the clock pulse φ₄ is controlled such thatthe potential below the charge transfer control gate electrode 22becomes higher than that below the storage gate electrode 21. Thebackground signal charges are removed by utilizing this potentialdifference.

That is, during the period from time T₃ to time T₄, the voltage of theclock pulse φ₁ is raised and a potential well is produced below the gateelectrode 12 and a part c of signal charges stored below the storagegate electrode 21 and below the charge transfer control gate electrode22 move to below the gate electrode 12. Then, the potential below thestorage gate electrode 21 and that below the charge transfer controlgate electrode 22 have a difference in their depth and therefore, signalcharges b, in accordance with the potential, remain below the storagegate electrode 21.

During the period from time T₄ to time T₅, the voltage of the clockpulse φ₅ is raised and the voltage of the clock pulse φ₄ is lowered.Accompanying therewith, the potential below the charge removing controlgate electrode 23 is lowered and the potential below the charge transfercontrol gate electrode 22 is raised. As a result, signal charges bremaining below the storage gate electrode 21 are drained through thedrain 24.

During the period from time T₅ to time T₆, the voltage of the clockpulse φ₃ is lowered and the potential below the storage gate electrode21 is raised. As a result, the signal charges below the storage gateelectrode 21 are completely drained. Further, the voltage of the clockpulse φ₂ is raised and a potential well is produced below the gateelectrode 13. As a result, signal charges stored at and below the gateelectrode 12 move also to and below the gate electrode 13.

During the period from time T₆ to time T₇, the voltage of the clockpulse φ₅ is lowered and the charge removal control gate electrode 23 israised. Thereby, the gate for draining the background signals is closed,i.e., off.

In this way, by controlling the voltage of the clock pulse φ₄ applied tothe charge transfer control gate electrode 22, it is possible to removethe background signal charges.

Next, a description is given of the control of the voltage of the clockpulse φ₄. At first, the front face of the photodetector is covered by apiece of black paper. Next, while the photodetector is usually operated,the voltage of the clock pulse φ₄ is changed and the output of thehorizontal CCD is output slightly. The value of the voltage of the clockpulse φ₄ is a value to be applied to the charge transfer control gateelectrode in order to remove the background signals.

The signal charges from which the background signal charges are removedare transferred to the horizontal CCD 3 in the vertical direction Signalcharges which are obtained by repeating the above-described operationare transferred to the horizontal CCD 3 from the vertical CCD 2 andtransferred on the horizontal CCD 3 to the output part 4.

A description is given of another embodiment of the present invention.

In this embodiment the removal of background signal charges is carriedout by the charge removal control gate electrode 23. The operation willbe described with reference to FIGS. 7 to 10.

In this case, the background signal charge removing part is a regionshown by 6' and at time T₁, the clock pulses φ₁ and φ₂ applied to thegate electrodes 10 and 11 are both at high voltages and a potential wellis produced at and below the gate electrodes 10 and 11 and signalcharges transferred by the vertical CCD 2 are stored thereat. Inaddition, a predetermined voltage is always applied to the chargeremoval control gate electrode 23 and the potential below the gateelectrode is lowered by a voltage corresponding to the voltage applied.

During the period from time T₁ to time T₂, the voltage of the clockpulse φ₁ is lowered and the voltage of the clock pulse φ₃ applied to thestorage gate electrode 21 is lowered. Accompanying therewith, thepotential well produced at and below the gate electrodes 10 and 11change as shown by T₂. As a result, the signal charges a move to belowthe gate electrodes 11 and 21. During the period from time T₂ to timeT₃, the voltage of the clock pulse φ₂ is lowered and signal charges a atand below the gate electrode 11 move to and below the storage gateelectrode 21. Then, the potential of the charge removal control gateelectrode 23 is a little lowered and the part of signal chargescollected at the storage gate electrode 21 exceeding the potential ofthe charge removal control gate electrode 23 pour out of the drain 24.The poured signal charges b are drained through the drain 24.

Accordingly, as similarly in the above-embodiment, by controlling thevoltage applied to the charge removal control gate electrode 23, it ispossible to remove a part of the signal charges a stored at and belowthe storage gate electrode 21. The signal charge amount to be removed ismade to coincide with the background signal charge amount by a methodsimilar to that described in the above-embodiment. Here in thisembodiment, in order to control the output, it is enough to control thevoltage applied to the charge removal control gate electrode 23. In thisway, signal charges c from which a part of signal charges are removedare stored at and below the storage gate electrode 21 as shown by T₃₋₄of FIG. 10.

Then during the period from time T₃ to time T₄, the voltage of the clockpulse φ₄ applied to the charge transfer control gate electrode 22 israised and as shown by time T₄ of FIG. 10, the signal charges at andbelow the storage gate electrode 21 move and signal charges are alsostored at and below the charge transfer control gate electrode 22.

During the period from time T₄ to time T₅, the voltage of the clockpulse φ₃ is lowered and the voltage of the clock pulse φ₁ applied to thegate electrode 12 is raised. Accompanying therewith, the potential belowthe gate electrode 12 changes as shown by time T₅ of FIG. 5 and as aresult, the signal charges move to and below the gate electrodes 22 and12.

During the period from time T₅ to time T₆, the voltage of the clockpulse φ₄ applied to the charge transfer control gate electrode 22 islowered. As a result, the potential changes as shown by time T₆ of FIG.10 and the movement of signal charges are carried out. The processing ofsignal charges thereafter is the same as that in the above-describedembodiment.

In the above-illustrated embodiment a one-dimensional solid-state imagerof one column is described, but in order to broaden the view field, aone-dimensional solid-state imager in which a plurarity of sets oflight-to-electricity conversion part 1, vertical CCD 2, transfer gate 4,and charge removing part 6 are arranged can be also constructed. In thiscase, however, the region in which the observed image is focused on theapparatus is lengthened in the row direction as shown in FIG. 11.Furthermore, the reading out, transfer, and removal of background signalcharges are carried out at the sam time for all sets, and the signalcharges read out from the respective vertical CCD 2 to the horizontalCCD 3 are sequentially output in the horizontal CCD from those close tothe output part. Thereby, a wide view one-dimensional solid-state imagerof high sensitivity is realized.

Furthermore, the background signal charge removal part 6 can be providedin an arbitrary number at arbitrary locations in the vertical CCD.

The sizes of the elements which are actually used are a pixel size of 30microns×20 microns, the pixel pitch in horizontal direction is about 60microns, and the pixel pitch in the vertical direction is about 30microns.

As is evident from the foregoing description, according to the presentinvention, a region for removing background signals is provided at avertical CCD between pixels and therefore a solid-state imagereffectively suppressing blooming without increasing the capacitance ofthe vertical CCD and thereby lowering the numerical aperture, andcarrying out a high sensitivity operation is obtained.

What is claimed is:
 1. A one-dimensional time-delay integrationsolid-state imager comprising:a semiconductor substrate; a plurality oflight-to-electricity conversion parts for storing signal chargesgenerated in response to incident light, said light-to-electricityconversion parts being arranged on said semiconductor substrate; avertical CCD disposed on said semiconductor substrate and including aplurality of stages extending from a first stage to a last stage, eachstage corresponding to one of said light-to-electricity conversionparts, said vertical CCD transferring signal charges stored atrespective light-to-electricity conversion parts; gate means forcontrolling transfer of signal charges stored at saidlight-to-electricity conversion parts to said corresponding stage ofsaid vertical CCD wherein signal charges corresponding to an observedimage moving across said plurality of light-to-electricity conversionparts are summed in said vertical CCD to enhance signal-to-noise ratio;and background signal charge removing means for removing backgroundsignal charges generated in response to background light, saidbackground signal charge removing means being disposed at anintermediate stage, between the first and final stages, of said verticalCCD and including:a storage gate electrode for storing chargestransferred from a preceding intermediate stage of said vertical CCD; acharge removal control electrode for draining background signal chargesfrom signal charges stored at said storage gate electrode in response toapplication of a pulse of a predetermined voltage to said charge removalcontrol electrode; and a charge transfer control gate electrode fortransferring charges from which background signal charges have beenremoved from said storage gate electrode to a subsequent stage of saidvertical CCD.
 2. A one-dimensional time-delay integration solid-stateimager comprising:a semiconductor substrate a plurality oflight-to-electricity conversion parts for storing signal chargesgenerated in response to incident light, said light-to-electricityconversion parts being arranged on said semiconductor substrate; avertical CCD disposed on said semiconductor substrate and including aplurality of stages extending from a first stage to a last stage, eachstage corresponding to one of said light-to-electricity conversionparts, said vertical CCD transferring signal charges stored atrespective light-to-electricity conversion parts; gate means forcontrolling transfer of signal charges stored at saidlight-to-electricity conversion parts to said corresponding stage ofsaid vertical CCD wherein signal charges corresponding to an observedimage moving across said plurality of light-to-electricity conversionparts are summed in said vertical CCD to enhanced signal-to-noise ratio;and background signal charge removing means for removing backgroundsignal charges generated in response to background light, saidbackground signal charge removing means being disposed at anintermediate stage, between the first and final stages, of said verticalCCD and including:a storage gate electrode for storing chargestransferred from a preceding, intermediate stage of said vertical CCD;and a charge removal control electrode for draining background signalcharges from signal charges stored at said storage gate electrodewherein a predetermined voltage is constantly applied to said chargeremoval control electrode to remove background signal charges.
 3. Aone-dimensional time-delay integration solid-state imager as defined inclaim 1 wherein the pulse of a predetermined voltage applied to saidcharge transfer control electrode is a voltage at which a slight outputis produced when there is no observed image incident on saidlight-to-electricity conversion parts.
 4. A one-dimensional time-delayintegration solid-state imager as defined in claim 2 wherein thepredetermined voltage constantly applied to said charge removal controlelectrode is a voltage at which a slight output is produced when thereis no observed image incident on said light-to-electricity conversionparts.